1. Field of the Invention
Embodiments of the present invention relate generally to static random access memory (SRAM) design and more specifically to a sequentially-accessed 1R/1W double-pumped single port SRAM with a shared decoder architecture.
2. Description of the Related Art
Integrated circuits commonly embed SRAM circuits to provide on-chip data storage. A given instance of an SRAM circuit is typically configured to meet specific design requirements associated with the surrounding circuitry attached to the SRAM. One common type of SRAM circuit provides one port for either read or write access to data stored within the SRAM. The address inputs to such a circuit are typically shared for both read and write access. Another common type of SRAM circuit, referred to as a two-port SRAM, provides two ports for accessing data stored within the SRAM. Two-port SRAM circuits usually restrict all read accesses to one port and all write accesses to the second port. Each port of a two-port SRAM is typically capable of asynchronous, independent access to data stored within the SRAM, allowing the two-port SRAM to be incorporated in a range of different applications with different usage models.
The two-port SRAM allows designers to achieve system performance levels that are generally higher than those possible using only one-port SRAM circuits. However, for a given number of storage bits, existing two-port SRAM circuits require approximately double the area of one-port SRAM circuits. Thus, integrated circuits where instances of SRAM circuits are a significant portion of the overall die area, using two-port SRAM circuits can be an extremely expensive design option.
One way to reduce the die area expense associated with using two-port SRAM circuits involves substituting each two-port SRAM circuit with a one-port SRAM circuit that operates at twice the access clock speed. By doubling the access clock speed, adequate read and write bandwidth may be provided. However, this solution involves generating an additional clock reference that is exactly twice the original clock frequency and generally requires substantial additional power. Furthermore, in high-performance designs, operating an SRAM at twice an already aggressive clock frequency may not be possible.
As the foregoing illustrates, what is needed in the art is a high-performance, area efficient two-port SRAM circuit design.